Generally, the industry of semiconductor manufacturing involves highly complex techniques for fabricating integrated circuits using semiconductor materials which are layered and patterned onto a substrate, such as silicon. Due to the large scale of circuit integration and the decreasing size of semiconductor devices, the fabricated devices have become increasingly sensitive to defects. That is, defects which cause faults in the device are becoming increasingly smaller. The device needs to be generally fault free prior to shipment to the end users or customers.
Defect detection is generally implemented across a full wafer for yield management in the semiconductor manufacturing industry. Types of defects, counts of defects, and signatures found by inspection systems (or inspectors) provide valuable information for semiconductor fabrication to ensure that the manufacturing process established in the research and development phase can ramp, that the process window confirmed in the ramp phrase can be transferrable to high volume manufacturing (HVM), and that day-to-day operations in HVM are stable and under-control.
An optical inspector is currently the only viable platform in the market to deliver enough speed to economically yield full wafer inspection. Full wafer coverage with an optical inspector has been implemented for HVM due to low expected defect counts on the wafer. In a mature process, the expected defect counts are typically less than 1000. Because of these low counts, combined with the mostly random locations of the defects across a 300 mm wafer, full wafer coverage with an optical inspector has been historically used to monitor the HVM process.
As design rule shrinks, however, the sensitivity gap between what is required for defect monitoring and what can be provided by optical inspector widens. This sensitivity gap is caused by the increasing disparity between critical dimension (CD) length and optical point spread function (PSF) size. The ratio between CD and optical PSF (CD:PSF) for a current design node is less than 1:10, and the CD:PSF ratio will continue to increase for subsequent generation design nodes. Because the CD:PSF ratio today is already 1:10, a single PSF can cover several design or defect structures. As a result, one generated optical signal can come from a single source (such as DOI) inside the PSF or multiple sources (such as a combination of DOI and wafer noise artifacts or just several wafer noise artifacts) inside the PSF. This effect causes ambiguity for defect detection. For example, a similar optical signal can be generated from a bridge type defect or different types of pattern edge placement error nuisances due to a large CD:PSF ratio. This effect creates ambiguity about how the optical signal is generated. As a result, an optical inspector is not able to differentiate certain defect signals from nuisance signals, which reduces optical inspector's ability to cleanly detect DOI's. Thus, current inspection systems and methodologies have a high sensitivity defect detection performance gap.
Accordingly, there is a continued demand for improved semiconductor wafer inspector systems and techniques